所有图书
Deepak Kumar Tala Verilog Tutorial (2003)(en)(123s)
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Deepak Kumar Tala Verilog Tutorial (2003)(en)(123s)
Verilog and SystemVerilog Gotchas: 101 Common Coding Errors and How to Avoid Them
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Verilog and SystemVerilog Gotchas: 101 Common Coding Errors and How to Avoid Them
Smith VHDL & Verilog Compared & Contrasted - Plus Modeled Example Written in VHDL, Verilog and C
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Smith VHDL & Verilog Compared & Contrasted - Plus Modeled Example Written in VHDL, Verilog and C
Quickstart Practical Guide to Simulation & Synthesis in Verilog
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Quickstart Practical Guide to Simulation & Synthesis in Verilog
Verilog HDL 高级数字设计 Advanced Digital Design with the Verilog HDL
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Verilog HDL 高级数字设计 Advanced Digital Design with the Verilog HDL
The Verilog PLI Handbook: A Users Guide and Comprehensive Reference on the Verilog Programming Language Interface
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The Verilog PLI Handbook: A Users Guide and Comprehensive Reference on the Verilog Programming Language Interface
IEEE Std 1364-2001: Verilog Hardware Description Language
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IEEE Std 1364-2001: Verilog Hardware Description Language
Verilog HDL Synthesis A Practical Primer
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Verilog HDL Synthesis A Practical Primer
Verilog HDL数字集成电路设计原理与应用
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Verilog HDL数字集成电路设计原理与应用
数字逻辑基础与Verilog设计 原书第3版
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数字逻辑基础与Verilog设计 原书第3版
Analog Behavioral Modeling with the Verilog-A Language
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Analog Behavioral Modeling with the Verilog-A Language
Verilog HDL 硬件描述语言 第二版 - J. Bhasker 著 徐振林 等译
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Verilog HDL 硬件描述语言 第二版 - J. Bhasker 著 徐振林 等译
The Verilog Hardware Description Language
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The Verilog Hardware Description Language
Sunsoft Press Verilog HDL A Guide to Digital Design and Synthesis
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Sunsoft Press Verilog HDL A Guide to Digital Design and Synthesis
Verilog for behavioral modeling
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Verilog for behavioral modeling
Verilog HDL: a guide to digital design and synthesis
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Verilog HDL: a guide to digital design and synthesis
搭建你的数字积木 数字电路与逻辑设计(Verilog HDL&Vivado版)
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搭建你的数字积木 数字电路与逻辑设计(Verilog HDL&Vivado版)
Verilog Quickstart: A Practical Guide to Simulation and Synthesis in Verilog
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Verilog Quickstart: A Practical Guide to Simulation and Synthesis in Verilog